This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-168615, filed Jun. 15, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a synchronous memory device using the techniques for accessing data items simultaneously in one cycle, or so-called prefetching techniques, and more particularly to the configuration of an address counter.
The recent trend of semiconductor memory technology has been toward using a DRAM with a special function for burst data transfer, such as a DRAM conforming to Rambus specifications or a synchronous DRAM (hereinafter, referred to as an SDRAM), in place of a conventional general-purpose DRAM in order to bridge the gap between the controller side including the CPU and MPU and the memory side. As for SDRAMs, Double Data Rate (DDR) specifications have been established and products conforming to the DDR specifications are going to be placed on the market. In the DDR specifications, not only the frequency of the basic clock (CLK) is raised, but also the input and output of data are synchronized with both of the leading edge and trailing edge of the basic clock as in a Rambus DRAM. In contrast, conventional Single Data Rate (SDR) specifications are such that the input and output of data are synchronized with the leading edge of the basic clock.
Now, consider the column accessing operation in a SDRAM. If the frequency of the basic clock is 100 megahertz, its period is 10 nanoseconds. In the case of SDR, the counting up of the address, column selection, and data transfer have to be performed in the 10-nanosecond period. Furthermore, when an attempt is made to increase the frequency of the basic clock or to carry out a DDR operation, a series of column access operations must be performed in the shortest time ranging from 3.5 to 4 nanoseconds. Even if a pipeline operation were performed or the manufacturing process of semiconductor devices were improved, the column accessing operation in such a short time would a very severe condition very difficult to satisfy using the present technology. Considering the fact that the CAS cycle time (tPC) of a conventional DRAM is about 12 to 15 nanoseconds, it is extremely difficult to realize such a short column accessing operation.
To solve this problem, a technique called prefetching has been introduced recently.
Semiconductor memory devices using the prefetching techniques have been disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-340579 and Jpn. Pat. Appln. KOKAI Publication No. 11-66878.
In the SDRAM, for example, when a column access operation is performed for reading, all the addresses to be accessed can be determined beforehand from the preset addressing mode and burst length at the time when the start address (hereinafter, referred to as the Tap address) supplied simultaneously with a read command is taken in. When the first Tap address is accessed, the subsequent addresses are accessed simultaneously, thereby reading part of the data, which gives a time margin to the column accessing operation of the second data item and later. Because a margin is given as CAS latency according to the SDRAM specifications to the time from when the read command is received until the data in the first Tap address is read, combining with a pipeline operation enables the data to be outputted continuously in a short cycle time. When too many bits have been prefetched, this makes timing control of the internal data lines complex. In addition, for example, a burst length smaller than the number of data items prefetched has been specified, the read-out data might be discarded uselessly. To avoid this, it is common practice to minimize the number of bits to be prefetched. From the viewpoint of the frequency of the present basic clock, two-bit prefetching has been considered to be able to cope with the cycle time sufficiently.
FIG. 1 is a block diagram of the address counter in a conventional semiconductor memory device without prefetching, which helps to explain the synchronous memory device. When the direction of depth of the column address is n+1 bits, the number of counters is n+1 from A less than 0 greater than  to A less than n greater than  (hereinafter,  less than n greater than  represents an accompanying character for bit order and  less than m:n greater than  indicates the consecutive bit orders from bit m to bit n, where m and n are integers). Signals ALTC less than n:0 greater than , CTCLK, TAPLTC, and INTLV are inputted to each of the counters 11-1 to 11-n. ALTC less than n:0 greater than  is a Tap address latched inside and is inputted to the counters 11-0 to 11-n corresponding to the accompanying characters. CTCLK is a clock signal for incrementing the counter and TAPLTC is a signal for transferring the Tap address. INTLV is a signal indicating an addressing mode. When the signal is at the high level, this means an interleave mode. When it is at the low level, this means a sequential mode. The counters 11-0 to 11-n for the respective bits output a counter address CA less than n:0 greater than  and at the same times a carry signal CRY less than nxe2x88x921:0 greater than  in such a manner that the counter address and carry signal are inputted to the counter at the next stage. At this time, the carry input to the counter 11-0 is fixed to a power supply (VDD) so that the counter may count up in each cycle. On the other hand, the carry of the counter 11-n is not outputted because there is no following stage.
FIG. 2 is a conceptual diagram showing the configuration of an address counter, which helps explain a conventional synchronous memory device that effects two-bit prefetching. To effect two-bit prefetching, two consecutive addresses are generally accessed and therefore two sets of counters 12A and 12B are needed. At the address input sections of the two sets of counters 12A and 12B, +1 adders 13A and 13B are provided, respectively. The output of an adder control circuit 14 determines which of the adders 13A and 13B is to be enabled.
Now, consider the operation of the adders 13A and 13B by reference to FIGS. 3A to 3D. In an SDRAM, two modes, the interleave mode and sequential mode, are defined as the addressing mode. FIGS. 3A and 3B show the interleave mode and FIGS. 3C and 3D show the sequential mode. In each mode, a total of four addressing patterns can be considered, depending on whether the Tap address is even (here, xe2x80x9c0000xe2x80x9d) or odd (here, xe2x80x9c001xe2x80x9d). In FIGS. 3A to 3D, three-bit addressing is shown for the sake of simplification. In each counter cycle, an even address whose least significant bit is xe2x80x9c0xe2x80x9d is written separately from an odd address whose least significant bit is xe2x80x9c1.xe2x80x9d
Two addresses written in one line (the part enclosed by a broken line) are assumed to be two-bit prefetched. In this case, the two sets of address counters 12A and 12B generate an even address and an odd address in each cycle, respectively. Of each counter set, the one-bit output corresponding to the low order is fixed to xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d and therefore is not needed. To effect three-bit addressing, the counter has only to contain two bits.
In the operation of the adders 13A and 13B in the interleave mode, when the Tap address is even (A less than 0 greater than =xe2x80x9c0xe2x80x9d), the address for the data to be read first is generated at the even counter and the address for the second data to be accessed simultaneously in two-bit prefetching is generated at the odd counter. At this time, because the counter address of the even counter is allowed to have the same value (000) as that of the Tap address, the adder on the even-number side need not operate and the Tap address has only to be transferred directly to the counter. The start address of the odd counter is such that the least significant bit is inverted in the Tap address (001). Since the least significant bit in the address has been fixed to xe2x80x9c1xe2x80x9d beforehand, the adder need not be operated and the remaining bits in the Tap address excluding the least significant bit have only to be transferred to the odd counter.
On the other hand, when the Tap address is odd (A less than 0 greater than =xe2x80x9c1xe2x80x9d), the address for the data to be read first is generated at the odd counter and the address for the second data is generated at the even counter. At this time, because the counter address of the odd counter is allowed to have the same value (001) as that of the Tap address, the adder on the odd-number side need not operate and the Tap address has only to be transferred directly to the counter. The start address of the even counter is such that the least significant bit is inverted in the Tap address (000). Since the least significant bit in the odd counter has been fixed to xe2x80x9c0,xe2x80x9d the adder need not be operated and the remaining bits in the Tap address excluding the least significant bit have only to be transferred to the even counter.
Next, consider the operation in the sequential mode. When the Tap address is even (A less than 0 greater than =xe2x80x9c0xe2x80x9d), the address for the data to be read first is generated at the even counter and the address for the second data is generated at the odd counter. At this time, because the counter address of the even counter is allowed to have the same value (000) as that of the Tap address, the adder on the even-number side need not operate and the Tap address has only to be transferred directly to the counter. The start address (001) of the odd counter is such that 1 is added to the Tap address. Since the least significant bit in the odd address has been fixed to xe2x80x9c1,xe2x80x9d the adder need not be operated and the remaining bits in the Tap address excluding the least significant bit have only to be transferred to the odd counter.
In contrast, when the Tap address is odd (A less than 0 greater than =xe2x80x9c1xe2x80x9d), the address for the data to be read first is generated at the odd counter and the address for the second data is generated at the even counter. At this time, because the counter address of the even counter is allowed to have the same value (001) as that of the Tap address, the adder on the odd-number side need not operate and the Tap address has only to be transferred directly to the counter. The start address (010) of the even counter is such that 1 is added to the Tap address. In this case, it is insufficient that the least significant bit in the even address has been fixed to xe2x80x9c0xe2x80x9d and therefore a judgment has to be made as to whether carry-over should be performed, checking all the bits in the Tap address. Therefore, in this case, the operation of the adder on the even-number side is needed.
It can be seen from the above-described operation that the adder on the odd-number side does not operate at all in the respective cases and therefore is unnecessary and the adder has only to be provided on the even-number side. It is only when the Tap address is odd in the sequential mode that the adder on the even-number side operates.
FIG. 4 is a conceptual diagram of a two-bit prefetch counter, taking into account what has explained above. There are two sets of counters for even numbers and odd numbers. The counter for the least significant bit in the bit number of each address is omitted and the hypothetical least significant bit address is fixed to either xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d At the address input section of an even counter 12Bxe2x80x2, there is provided a +1 adder 13B controlled by the adder control circuit 14. The adder 13B operates in such a manner that, when the addressing mode is the sequential mode and the least significant bit in the Tap address is xe2x80x9c1,xe2x80x9d the start address in the counter 12Bxe2x80x2 becomes Tap address+1.
FIG. 5 is a block diagram of a two-bit prefetch n-bit counter actually constructed on the basis of the conceptual diagram of FIG. 4. Two sets of counters for odd numbers and even numbers from A less than 1 greater than  to A less than n greater than  excluding A less than 0 greater than , the least significant bit, are provided. The adder control circuit 14 senses that the sequential mode is on and the Tap address is odd and generates an odd control signal EvenCtrl less than 1:n greater than  for each bit. The +1 adders 13B-1 to 13B-n are provided at the preceding stages of the odd counters 12B-1 to 12B-n and transfer the Tap address as it is or invert it (or add 1 to the Tap address) and transfer the inverted address.
Of the signals ALTC less than n:0 greater than , CTCLK, TAPLTC, and INTLV inputted to each circuit, ALTC less than n:0 greater than  is the Tap address latched inside and is inputted to the counter with the corresponding accompanying character. The signal ALTC less than 0 greater than  of the least significant bit is inputted to the adder control circuit 14. CTCLK is a clock signal for incrementing the counters 12A-1 to 12A-n and 12B-1 to 12B-n and TAPLTC is a signal for transferring the Tap address to the inside of the counter. INTLV is a signal indicating the addressing mode. When this signal is high, this means the interleave mode. When the signal is low, this means the sequential mode.
The respective bits of the counters 12A-1 to 12A-n output odd counter addresses CAo less than 1:n greater than  and the respective bits of the counters 12B-1 to 12B-n output even counter addresses CAe less than 1:n greater than . At the same time, the counters 12A-1 to 12A-n and 12B-1 to 12B-n output carry signals CRYo less than 1:nxe2x88x921 greater than  and CRYe less than 1:nxe2x88x921 greater than , respectively. The carry signals CRYo less than 1:nxe2x88x921 greater than  and CRYe less than 1:nxe2x88x921 greater than  are inputted sequentially to the counters at the next stages. The carry input to the counters 12A-1 and 12B-1 corresponding to A less than 1 greater than  is fixed to the power supply (VDD) so that the counters count up in each cycle. The counters 12A-n and 12B-n corresponding to A less than n greater than  do not output any carry because they has no subsequent stage.
An example of the configuration of each of the counters 12A-1 to 12A-n and 12B-1 to 12B-n is shown in FIG. 6. An example of the configuration of each of the +1 adders 13B-1 to 13B-n is shown in FIG. 7. An example of the configuration of the adder control circuit 14 is shown in FIG. 8.
As shown in FIG. 6, each of the counters 12A-1 to 12A-n and 12B-1 to 12B-n is composed of three sections: a counter section 15, a Tap input section 16, and a carry operation section 17. FIG. 6 focuses on the counter 12A-i (or 12B-i) at the i-th (ixe2x88x921 to n) stage. The counter section 15 includes an exclusive OR gate 21, clocked inverters 22 to 25, and inverters 26 and 27. The Tap input section 16 is composed of clocked inverters 28 and 29. The carry operation section 17 includes inverters 30 to 33, an NOR gate 34, an exclusive OR gate 35, and a NAND gate 36. A Tap loading signal TAPLTC is supplied to the inverter 37, which produces its inverted signal bTAPLTC. A clock signal CTCLK is supplied to the inverter 38, which produces its inverted signal bCTCLK.
According to the Tap loading signals TAPLTC, bTAPLTC, the Tap input section 16 loads the start address TAP into the counter section 15 and carry operation section 17. According the carry signal CRY less than i-1 greater than  and clock signal CTCLK from the counter at the preceding stage, the counter section 15 counts up the counter address CA less than i greater than  sequentially. Furthermore, the carry operation section 17 generates a carry signal CRY less than i greater than  for controlling the timing with which the counter at the following stage counts up in the addressing mode.
As shown in FIG. 7, each of the +1 adders 13B-1 to 13B-n is composed of two CMOS transfer gates 39 and 40 and inverters 41 and 42. When signal EvenCtrl is at the low level, the adder outputs signal ALTC directly as signal TAP. When signal EvenCtrl is at the high level, the adder inverts signal ALTC and outputs the inverted signal as signal TAP.
Furthermore, as shown in FIG. 8, the adder control circuit 14 includes an inverter 43, NAND gates 44-1 to 44-n, and inverters 45-1 to 45-n. The adder control circuit 14 receives signal INTLV and Tap address and makes high the signals EvenCtrl all the way to the NAND gates where the Tap address in the individual bits inputted are all xe2x80x9c1,xe2x80x9d with signal INTLV at the low level, or in the sequential mode. Naturally, the remaining signals EventCtrl are all at the high level.
In those configurations, the start address in each of the counters 12A-1 to 12A-n and 12B-1 to 12B-n will be explained. First, in the configuration of FIG. 5, since Tap address ALTC less than 1:n greater than  is inputted directly to the odd counters 12A-1 to 12A-n, the start address is the same as the Tap address, regardless of the case. As for the even counters 12B-1 to 12B-n, when the addressing mode is the interleave mode, all the EvenCtrl signals of the adder control circuit 14 are at the low level, causing the transfer gates 39 for the adders 13B-1 to 13B-n to open, which allows the Tap address to become the start address without any change. When the addressing mode is the sequential mode, signal INTLV is low, which causes the adder control circuit 14 to decode the Tap address. If signal ALTC less than 0 greater than  is xe2x80x9c0xe2x80x9d (Tap address is odd), all the EvenCtrl signals are at the low level, allowing the Tap address to become the start address without any change as in the interleave mode. Moreover, when signal ALTC less than 0 greater than  is xe2x80x9c1xe2x80x9d (Tap address is odd), at least signal EvenCtrl less than 1 greater than  is at the high level and the bits in the signals EvenCtrl that go high according to the states of the higher-order bits change. For example, when signal ALTC less than 0:n greater than  is 110 . . . 0, signal EvenCtrl less than 1:2 greater than  is high and signal EvenCtrl  less than 3:n greater than  is low. Even control signal EvenCtrl less than n greater than  for the n-th bit is generally expressed by the following equation (1):
EvenCtrl less than n greater than =/INTLVxc2x7AILTC less than 0:nxe2x88x921 greater than xe2x80x83xe2x80x83(1)
where signal /INTLV is the inverted signal of INTLV.
Therefore, the Tap address is inputted as it is to the even counters 12B-3 to 12B-n and the inverted one is inputted to the even counters 12B-1 and 12B-2. Specifically, the start address inputted to the even counters 12B-1 to 12B-n is 001 . . . 0, which is the value obtained by adding 1 to the Tap address.
Next, the operation timing of the counters shown in FIG. 6 will be explained by reference to FIGS. 9A and 9B and FIGS. 10A and 10B. These timing charts help explain the operation of counter 12A-2 as a representative of the counters. As shown in FIGS. 3A to 3D, there are a total of four types of addressing.
FIGS. 9A and 9B show the operation timing in the sequential mode and FIGS. 10A and 10B show the operation timing in the interleave mode. Moreover, FIGS. 9A and 10A show the operation timing when TAP less than i greater than =xe2x80x9c0.xe2x80x9d FIGS. 9B and 10B show the operation timing when TAP less than i greater than =xe2x80x9c1.xe2x80x9d
First, FIGS. 9A and 9B will be described. When the addressing mode is the sequential mode, the operation of the carry operation section 17 is simple. Since signal INTLV is low, TPR less than i greater than  is fixed to the high level, causing the value of CAR less than i greater than  to be equal to that of CA less than i greater than , regardless of the state of TAP less than i greater than . When a column command is received and the Tap address is determined, signal TAPLTC goes high (from time t1 to time t2). Then, the counter section 15 takes in TAP less than i greater than . At this time, because clock signal CTCLK is still low, the TAP less than i greater than  passes through CAX less than i greater than  and is outputted as it is to CA less than i greater than . Next, even when signal TAPLTC goes low (at time t2) and clock signal CTCLK goes high, the value of CA less than i greater than  is loaded into the master stage again because carry signal CRY less than ixe2x88x921 greater than  from the preceding stage is low, with the result that the state of CAX less than i greater than  remains unchanged. Furthermore, when clock signal CTCLK goes low (at time t3), the value of CAX less than i greater than  is transferred. At this time, since CAX less than i greater than  remains unchanged, thus the value of CAX less than i greater than  remains unchanged. On the other hand, because carry signal CRY less than ixe2x88x921 greater than  from the counter at the preceding stage goes high at that time, as soon as clock signal CTCLK goes high at the next time t4, the value of CAX less than i greater than  is inverted. Furthermore, when clock signal CTCLK goes low at time t5, CA less than i greater than  is inverted. Hereinafter, similarly, at time t6, neither CAX less than i greater than  nor CA less than i greater than  changes. At time t7, carry signal CRY less than ixe2x88x921 greater than  goes high, permitting CAX less than i greater than  to be inverted at the next time t8. At time t9, CA less than i greater than  is inverted. From this time on, those operations are repeated, thereby causing the counter to count up.
The carry signal CRY less than i greater than  the counter outputs is equal to the AND of carry signal CRY less than ixe2x88x921 greater than  at the preceding stage and CA less than i greater than  because the value of CAR less than i greater than  is always equal to the value of CA less than i greater than . As shown in FIG. 9A, when TAP less than i greater than =xe2x80x9c0,xe2x80x9d the carry signal CRY less than i greater than  is high from time t7 to time t9 during the time when both CA less than i greater than  and CRY less than ixe2x88x921 greater than  are high. Moreover, as shown in FIG. 9B, when TAP less than i greater than =xe2x80x9c1,xe2x80x9d the carry signal CRY less than i greater than  is high from time t3 to time t5.
In the interleave mode shown in FIGS. 10A and 10B, the operation of the counter section is the same as in the sequential mode and therefore its explanation will be omitted. Only one thing that differs is the operation of the carry operation section 17. Specifically, since signal INTLV is high, the value of TPR less than i greater than  is equal to the value of TAP less than i greater than  taken in from time t1 to time t2. The EXOR (exclusive OR) (CAR less than i greater than  ) of the signal and counter address CA less than i greater than  is ANDed with CRY less than ixe2x88x921 greater than . The resulting signal is a carry signal CRY less than i greater than . Specifically, when CA less than i greater than  makes its round of TAP less than i greater than  and is inverted and the carry signal CRY less than ixe2x88x921 greater than  at the preceding stage goes high, a carry signal is outputted. Therefore, the CRY less than i greater than  is outputted from time t7 to time t9, regardless of whether TAP less than i greater than  is either xe2x80x9c0xe2x80x9d or xe2x80x9c1.xe2x80x9d
Although a two-bit prefetch address counter can be constructed as described above, use of prefetching techniques to secure a margin for cycle time or access time makes it necessary to prepare as many bits as are needed to prefetch the sets of address counters as seen from FIG. 5. In an SDRAM, when the Full Page mode is considered, an address counter containing as many bits (e.g., 10 bits for 1000 columns) as correspond to the direction of depth of column address is needed, even if prefetching is not done. If two-bit prefetching is implemented, twice (e.g., 9 bitsxc3x972=18 for 1000 columns) as many address counters as correspond to the number of bits excluding the least significant bit are needed.
Although prefetching techniques have the merit of making the column access operation faster, such problems as an increase in the number of circuits or the circuit area arise. Since those address counters are generally shared in a single chip, it is desirable that they should be arranged in places at as equal distances from the respective banks as possible to equalize the delay time to each bank. Such places, however, are often very important area to the other principal circuits from the viewpoint of characteristics. Thus, placing many address counters is by no means favorable from the standpoint of the characteristics of the entire chip.
As described above, in the conventional synchronous memory device using prefetching techniques to cope with a high-frequency basic clock and highspeed data accessing according to DDR specifications, an increase in the number of circuits or the circuit area in the address counters has become a problem.
It is, accordingly, an object of the present invention to provide a synchronous memory device which operates at high speed and is excellent in its operating characteristics.
Another object of the present invention is to provide a synchronous memory device capable of suppressing an increase in the number of circuits and the circuit area of the address counters even when using prefetching techniques, thereby reducing the chip area.
The foregoing objects are accomplished by providing a synchronous memory device with a prefetch address counter for accessing data items in a single cycle, the address counter comprising: an n number of one-bit counter circuits to each of which a start address supplied simultaneously with a read command, a clock signal for incrementing a count value, a signal for transferring the start address to the inside of the counter, and a signal indicating an addressing mode are supplied, and the first stage of which counts up in each cycle, thereby causing a carry signal to be inputted to the following stage one after another; an adder control circuit to which an addressing mode signal indicating the state of the addressing mode and the outputs of the n one-bit counter circuits are supplied and which senses that the addressing mode is the sequential mode and the start address is an odd address and generates an even control signal for each bit; and an n number of adders which are provided so as to correspond to the one-bit counter circuits and which, according to the state of the even control signal outputted from the adder control circuit, invert the address outputted from each of the one-bit counter circuits when the addressing mode is the sequential mode and the start address is an odd address, but otherwise output the same signal as the address outputted from each of the one-bit counter circuits, wherein the n one-bit counter circuits and the n adders output n-bit addresses.
With the above-described configuration, even when prefetching is used, the number of one-bit counters needed is n, which is half the number of one-bit counters needed for a conventional equivalent, or 2xc3x97n. Furthermore, since the conventional equivalent needed n+1 one-bit counters even when prefetching is no used, the number of one-bit counters is reduced by one. If the number of bits is small, a decrease in the circuit area as a result of a decrease in the number of one-bit counters is greater than an increase in the chip area as a result of providing adders. Therefore, it is possible to provide a synchronous memory device capable of decreasing the chip area by suppressing an increase in the number of address counter circuits and in the circuit area. Furthermore, it is possible to provide a synchronous memory device which operates at high speed and is excellent in its operating characteristics as a result of effecting prefetching to cope with high-frequency basic clocks and high-speed data accessing according to, for example, DDR specifications.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.